The AMALTHEA hardware model is used to describe hardware systems which usually consists of ECUs, microcontrollers, cores, memories, additional peripherals etc. It is central accessible through the HWModel element and contains following elements:
A reduced overview of the Meta Model specifying the Hardware Model is shown below. The overall hierarchy within this model is represented by blue classes (HwSystem, ECU, Microcontroller and Core). Red classes indicate type descriptions which contain the parameters of their referencing elements, e.g. it is possible to specify a type of a core with all relevant attributes which will be referenced by core instances. This supports quick modeling of homogeneous architectures and increases the reutilization of already described hardware. Green classes represent additional hardware peripherals which can be described on each of the hardware hierarchies (HwSystem, ECU, Microcontroller and Core).
The structure of descriptions regarding the network is shown in the following figure. The ComplexNode and each of its specializations (e.g. HwSystems, ECUs, Networks, ...) may contain a list of HwPort elements. The ComplexPort element is a specialization which is attached to exactly one network. More detailed descriptions about the respective elements are given in the following section.
The ComplexNode is the generalization of all hardware components. It holds the described components name and contains its nested hardware elements, e.g. memories, networks, ports etc.
| Attribute | Type | Mul. | Valid Values | Description |
|---|---|---|---|---|
| quartzes | Containment | * | Quartz | Containment for Quartz objects (i.e. frequency generators) located on the specialization of this element. |
| prescaler | Containment | * | Prescaler | Containment for Prescaler (i.e. frequency prescaler) objects located on the specialization of this element. |
| memories | Containment | * | Memory | Containment for Memory (i.e. memories, such as RAM or ROM) objects located on the specialization of this element. |
| networks | Containment | * | Network | Containment for Network (i.e. networks, such as LIN, CAN or ETHERNET) objects located on the specialization of this element. |
| components | Containment | * | HwComponent | Containment for HwComponent (i.e. all other entities of hardware) objects located on the specialization of this element. |
| ports | Containment | * | HwPort | Containment for HwPort (i.e. interfaces with multiple pins) objects located on the specialization of this element. |
The HwSystem is a specialization of the ComplexNode and represents a cluster of one or more ECU elements which in sum implement a specific system.
| Attribute | Type | Mul. | Valid Values | Description |
|---|---|---|---|---|
| systemType | Reference | 1 | SystemType | Refers to a SystemType containing the configuration for this system. |
| ecus | Containment | + | ECU | Containment for Electronic Control Units ( ECU) that are part of this system. |
The ECU (Electronic Control Unit) is a specialization of the ComplexNode and represents any physical electronic hardware on an embedded system level abstraction level.
| Attribute | Type | Mul. | Valid Values | Description |
|---|---|---|---|---|
| ecuType | Reference | 1 | ECUType | Refers to a ECUType containing the configuration for this ECU. |
| microcontrollers | Containment | + | Microcontroller | Containment for Microcontrollers that are part of this ECU. |
The Microcontroller is a specialization of the ComplexNode and represents any physical hardware on System on Chip abstraction level, e.g. processors with one or more special or generic purpose cores.
| Attribute | Type | Mul. | Valid Values | Description |
|---|---|---|---|---|
| microcontrollerType | Reference | 1 | MicrocontrollerType | Refers to a MicrocontrollerType containing the configuration for this microcontroller. |
| cores | Containment | + | Core | Containment for processing cores ( Core) that are part of this microcontroller. |
The Core is a specialization of the ComplexNode and represents the respective processing units on any type of single- or multi core processor.
| Attribute | Type | Mul. | Valid Values | Description |
|---|---|---|---|---|
| coreType | Reference | 1 | CoreType | Refers to a CoreType containing the configuration for this core. |
| lockstepGroup | Integer | ? | 0 – 255 | If set, this value defines the lockstep group of the core. All cores with the same lockstep group are operating in lockstep mode together. |
The
Memory is a specialization of the
ComplexNode and represents memories. It is used to describe any type of memory module, e.g. Flash, RAM, etc.
Please note that to specify a memory with the type
CACHE (e.g. lv1 cache as part of a core) it is sufficient to specify it within a core. It is not necessary to specify additional networks or ports.
| Attribute | Type | Mul. | Valid Values | Description |
|---|---|---|---|---|
| type | Reference | 1 | MemoryType | Refers to a MemoryType containing the configuration for this memory. |
The Network is a specialization of the ComplexNode and represents networks of interconnected ComplexPort elements.
| Attribute | Type | Mul. | Valid Values | Description |
|---|---|---|---|---|
| type | Reference | 1 | NetworkType | Refers to a NetworkType containing the configuration for this network. |
The Quartz is a specialization of the ComplexNode and represents a frequency generator which may be located on any ComplexNode or its specializations. It may be referenced by any number of Prescalers.
| Attribute | Type | Mul. | Valid Values | Description |
|---|---|---|---|---|
| type | QType | 1 | STATIC / DYNAMIC | Specifies if the Quartz operates at either a static or dynamic frequency. |
| frequency | Integer | ? | 0 – 255 | Frequency on which this Quartz is operating. |
The Component (or HwComponent) is a specialization of the ComplexNode and represent hardware elements which are not further specified. They may contain any number of nested Components.
| Attribute | Type | Mul. | Valid Values | Description |
|---|---|---|---|---|
| nestedComponents | Containment | 1 | HwComponent | Containment for HwComponent (i.e. all other entities of hardware) objects located below this component. |
The abstract class HardwareTypeDescription is the generalization of all type description for memories, cores, ECUs, networks etc. It allows its specializations to stor information about their features.
The abstract class AbstractionTypeDescription is a specialization of the HardwareTypeDescription and generalization for hardware types which describe hardware abstraction, i.e. the HwSystem, ECU, Microcontroller and Core.
The SystemType is a specialization of the AbstractionTypeDescription and used to define a specific type of a system. If multiple systems with the same characteristics exist, it is sufficient to define only one type and reference it by all systems sharing the same type.
The ECUType is a specialization of the AbstractionTypeDescription and used to define a type of an ECU.
The MicrocontrollerType is a specialization of the AbstractionTypeDescription and used to define a type of a Microcontroller.
The CoreType is a specialization of the AbstractionTypeDescription and used to define a type of a Core, i.e. its bit width and ticks per cycle.
| Attribute | Type | Mul. | Valid Values | Description |
|---|---|---|---|---|
| bitWidth | Integer | 1 | 0-255 | The cores architectures bit width (e.g. 32 or 64 bit) |
| instructionsPerCycle | Integer | 1 | 0-255 | Number of processed (computed) instructions per cycle. |
The MemoryType is a specialization of the HardwareTypeDescription and used to define a type of a memory, i.e. its size, access pattern and type.
| Attribute | Type | Mul. | Valid Values | Description |
|---|---|---|---|---|
| xAccessPattern | String | 1 | String | Timing Architects specific value. Will be used in the future to determine the access pattern of a memory element. |
| type | MemoryType | 1 | RAM/CACHE/FLASH_INT/FLASH_EXT | Specifies the type of this Memory. |
| size | Long | 1 | >0 | Size of this memory. |
The NetworkType is a specialization of the HardwareTypeDescription and used to define a type of a Network, i.e. max supported bit width and scheduling policy.
| Attribute | Type | Mul. | Valid Values | Description |
|---|---|---|---|---|
| schedPolicy | SchedType | 1 | RROBIN/PRIORITY | Specifies the scheduling policy which is used on this Network. |
| bitWidth | Integer | 1 | 0 – 255 | Specifies the max bit width that may be transferred on this network per cycle. |
The CrossbarSwitch is a specialization of a NetworkType and represents switches, which allow simultaneous/concurrent connections between all types of components
| Attribute | Type | Mul. | Valid Values | Description |
|---|---|---|---|---|
| conConnections | Integer | 1 | 0 – 255 | Maximum number of concurrent 1:n connections |
The Bus is a specialization of the NetworkType and represents any kind of bus network, e.g. CAN, LIN etc.
| Attribute | Type | Mul. | Valid Values | Description |
|---|---|---|---|---|
| type | BusType | 1 | CAN/TTCAN/LIN/FLEXRAY/ETHERNET/SPI/NA | Specifies the type of the bus network. |
The Bridge is a specialization of a NetworkType and represents bridges or gateways. It is used to transfer data from one network to another and performs a one-way translation, e.g. a ComplexNode containing a Bridge is accessed by its ComplexPort and routes the data to its containing Bridge. If a ComplexNode contains more than one Bridge, the respective target network is determined by the address range of its connected ComplexPort elements.
The Pin represents a single pin and serves as abstract representation for pure informative use, e.g. by a developer describing a port.
The ComplexPin is a specialization of the Pin and contains detailed information, i.e. the type of the pin, its address and its direction (read/write).
| Attribute | Type | Mul. | Valid Values | Description |
|---|---|---|---|---|
| type | PinType | 1 | ANALOG/DIGITAL | Specifies if this pin is either operating in analog or digital mode |
| baseAddress | Long | 1 | >= 0 | Specifies the address of this pin, i.e. the address this pin is accessed by. |
| direction | RWType | 1 | R/W/RW | Specifies the direction the data may travel through this pin, e.g. ®ead only, (W)rite only or both (RW). |
The Port represents groups of pins and may be used to describe simple interfaces, e.g. 8-bit ports etc. Its main purpose is to describe ports which only serve informative use.
The ComplexPort is a specialization of the Port and represents interfaces on any type of ComplexNode which are connected to a Network.
| Attribute | Type | Mul. | Valid Values | Description |
|---|---|---|---|---|
| network | Reference | 1 | Network | References the network which this ComplexPort is a part of. Only ComplexPorts attached to the same network are capable of communicated directly with each other. If data is transfered over multiple networks, either a valid route (e.g. Port A -> Network A -> Port B and Port C -> Network B -> Port D, with Ports B and C beeing on the same device), or an access path have to be present. |
| isMaster | Boolean | 1 | TRUE/FALSE | Specifies if this ComplexPort may send requests to a Network (e.g. a processor) or just answer them (e.g. a memory). |
| bitWidth | Integer | 1 | >0 | Specifies the max bit width that may be transferred via this ComplexPort. |
| baseAddress | Long | 1 | >0 | Specifies the base address of this ComplexPort, making it addressable through other ComplexPorts in the Network. |
| addressRange | Long | 1 | >0 | Specifies the size of the addressable area this ComplexPort is addressed by. The address space is determined by the baseAddress offset and this value. |
| direction | RWType | 1 | R/W/RW | Specifies the direction the data may travel through this port, e.g. ®ead only, (W)rite only or both (RW). Note that the direction is always related to the isMaster attribute, e.g. Master ports read and write TO the network, while non-master ports are read and written BY the network. |
| readCycles | Integer | 1 | >0 | Specifies the number of cycles until a read is performed. |
| writeCycles | Integer | 1 | >0 | Specifies the number of cycles until a write is performed. |
| schedValue | Integer | 1 | >0 | Optional parameter for the usage in network scheduling policies. The meaning of this attribute depends on the used schedulingPolicy of the referenced Network, e.g. it may be the priority in a priority scheduled network or the order in a round robin scheduled network. |
The AbstractType is an abstract class, allowing attributes to describe data without specifying their data type. It contains the field name to specify the name of the value while the specializations BoolValue, CharValue, IntValue, LongValue, DoubleValue and StringValue contain the resp. value types.
The
AccessPath element describes in general the needed time in cycles for a hardware element (
ComplexNode) A to access a hardware element B.
It can be configured in two different ways:
Both approaches includes the possibility to reference another given path of the same type, so it is possible for example to describe sub paths, which are then included in a main path.
The following picture shows the structure of these two approaches:
To describe a latency for a given core a memory, only these elements are needed inside of the Hardware model.
The next picture shows a simple overview of a core, which is able to access two memories with different latencies.
Using the provided AMALTHEA model editor this small sample would look like the following picture:
Using the HwAccessPath element to describe an access path, the included elements must be available with the proper ComplexPorts. The access path consists with a list of elements, which are referencing existing ports.
The next overview shows a very simple sample, with a core and two memories connected using a network and the proper ports.
Configuring the two access paths from Core1 to Memory1 and to Memory2 results in two HwAccessPaths containing the proper ports, showed in the next overview.
