12.6 Finite State Machines

12.6.1 Description

Definition from Wikipedia:

A finite-state machine (FSM) or finite-state automaton (plural: automata), or simply a state machine, is a mathematical model used to design computer programs and digital logic circuits. It is conceived as an abstract machine that can be in one of a finite number of states. The machine is in only one state at a time; the state it is in at any given time is called the current state. It can change from one state to another when initiated by a triggering event or condition, this is called a transition. A particular FSM is defined by a list of the possible states it can transition to from each state, and the triggering condition for each transition.

In ROOM each actor class can implement its behavior using a state machine. Events occurring at the end ports of an actor will be forwarded to and processed by the state machine. Events possibly trigger state transitions.

12.6.2 Motivation

For event driven systems a finite state machine is ideal for processing the stream of events. Typically during processing new events are produced which are sent to peer actors.

We distinguish flat and hierarchical state machines.

12.6.3 Notation

Flat Finite State Machine

The simpler flat finite state machines are composed of the following elements:


Table 12.6: Title



Description Graphical Notation Textual Notation



State PIC PIC



InitialPoint PIC implicit



TransitionPoint PIC PIC



ChoicePoint PIC PIC



Initial Transition PIC PIC



Triggered Transition PIC PIC




Hierarchical Finite State Machine

The hierarchical finite state machine adds the notion of a sub state machine nested in a state. A few modeling elements are added to the set listed above:


Table 12.7: Title



Description

Graphical Notation Textual Notation



State with sub state machine

Parent State
PIC
Sub state machine
PIC



Entry Point

In sub state machine
PIC
PIC



Exit Point

PIC




12.6.4 Examples

Example of a flat finite state machine:

PIC

Example of a hierarchical finite state machine:

Top level

PIC

Sub state machine of Initializing

PIC

Sub state machine of Running

PIC